[meta-xilinx] SPI problem
mike.looijmans at topic.nl
Thu May 11 05:57:21 PDT 2017
On 11-05-17 14:31, Arno Steffens wrote:
>> Gesendet: Donnerstag, 11. Mai 2017 um 07:24 Uhr
>> Von: "Mike Looijmans" <mike.looijmans at topic.nl>
>> An: "Nathan Rossi" <nathan at nathanrossi.com>, "Arno Steffens" <star at gmx.li>
>> Cc: meta-xilinx at yoctoproject.org
>> Betreff: Re: [meta-xilinx] SPI problem
>> On 10-05-17 15:23, Nathan Rossi wrote:
>>> On 10 May 2017 at 17:18, Arno Steffens <star at gmx.li> wrote:
>>>> Thanks Mike for the feedback.
>>>> It is an OnSemi Phyton camera chip.
>>>> Unfortunately FPGA is not suitable solution for me. The layout is already fixed and I am not an FPGA expert.
>>>> Checking the SPI registers in Technical Manual: it seems that there is no separate setting for CPOL/CPH for MOSI and MISO.
>>>> The only way I see is to send address, keep CS low, change SPI mode, read.
>>>> But there is another limitation. In struct spi_ioc_transfer there is a setting: bits_per_word. I need 10 for doing that
>>>> as described for the first part (9 bit adress + 1 r/w bit). This returns an error "could not transmit data". Any value expect 8 is returning an error.
>>>> Is this a limitation by hardware or an issue in driver, which can be fixed?
>>> For the Zynq PS SPI controllers there is a hard limit to 8-bit words
>>> (kernel driver advertises this here:
>>> If you need 10b words and you do not want to do it with an FPGA
>>> device, you can always use the kernels spi-bitbang module. But this is
>>> likely only good for low bandwidth control SPI, so if you are using
>>> SPI to pull image data from the camera this is probably not what you
>>> want. Also you could easily modify the spi-bitbang module to handle
>>> this CPOL inversion, such that it always samples MISO on the falling
>> Camera chips usually only use the SPI interface for configuration, so I'd go
>> with Nathan's suggestion and use Linux' bit-bang SPI controller for setting
>> camera parameters and such. Let the kernel pinmix the pins as GPIO and assign
>> them via devicetree to the bitbang controller.
>> Kind regards,
>> Mike Looijmans
>> System Expert
> In fact it is just for configuration.
> Thanks, so it is clear that I can't hope to solve it without changing the bitstream (although remapping is not a big deal). Do you have an idea what frequency can be achieved by this driver?
> And I am a bit afraid of negative side-effect to more "realtime" related stuff on ARM.
I'd expect something in the 100kHz..1MHz range for the SPI bus. Changes to
FPGA are only needed if the component is connected through logic. In which
case it'd be better to completely solve it in logic and put a custom SPI (ish)
controller in the FPGA that handles this chip. If SPI is connected through MIO
pins, no change in logic is required (or possible actually).
I'm not too worried about the impact on other stuff, the SPI bitbang task can
probably be pre-emted by any other task. I'm always using a bitbang I2C
controller on the Zynq (because the hardware is broken) and haven't seen any
negative effects on timing from that either.
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