[meta-xilinx] SPI problem

Nathan Rossi nathan at nathanrossi.com
Wed May 10 06:23:29 PDT 2017

On 10 May 2017 at 17:18, Arno Steffens <star at gmx.li> wrote:
> Thanks Mike for the feedback.
> It is an OnSemi Phyton camera chip.
> Unfortunately FPGA is not suitable solution for me. The layout is already fixed and I am not an FPGA expert.
> Checking the SPI registers in Technical Manual: it seems that there is no separate setting for CPOL/CPH for MOSI and MISO.
> The only way I see is to send address, keep CS low, change SPI mode, read.
> But there is another limitation. In struct spi_ioc_transfer there is a setting: bits_per_word. I need 10 for doing that
> as described for the first part (9 bit adress + 1 r/w bit). This returns an error "could not transmit data". Any value expect 8 is returning an error.
> Is this a limitation by hardware or an issue in driver, which can be fixed?

For the Zynq PS SPI controllers there is a hard limit to 8-bit words
(kernel driver advertises this here:

If you need 10b words and you do not want to do it with an FPGA
device, you can always use the kernels spi-bitbang module. But this is
likely only good for low bandwidth control SPI, so if you are using
SPI to pull image data from the camera this is probably not what you
want. Also you could easily modify the spi-bitbang module to handle
this CPOL inversion, such that it always samples MISO on the falling


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