[meta-freescale] cannot configure divider when PLL is powered on
festevam at gmail.com
Sun Mar 4 13:14:35 PST 2018
On Thu, Feb 1, 2018 at 7:08 AM, Vishnu Motghare
<vishnumotghare at gmail.com> wrote:
> I'm using i.MX6 board which has dw-hdmi Synopsys DesignWare HDMI Controller.
> I 'm using linux-3.10 kernel version which doesn't have DRM support for
> Synopsys. So, I back ported drm driver from linux-4.8.
> Driver probed happend successfully. Following is dmesg
> [ 1.642015] imx-drm display-subsystem: bound 120000.hdmi (ops
> [ 1.649845] imx-drm display-subsystem: bound
> 2000000.aips-bus:ldb at 020e0008 (ops imx_ldb_ops)
> I got following error,
> imx-ldb ldb.15: unable to set di1 parent clock to original parent
> So' I ported following patch from mainline kernel,
> After this I'm getting following error,
> clk_pllv3_set_rate: cannot configure divider when PLL is powered on
> I'm not getting any clue to fix this error. Doen any other patch is required
> to fix this issue?
This is a bit off-topic for the list.
Why do you use 4.8 kernel, which is no longer supported?
You should use 4.15.7 instead.
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