Understanding pads setup
Mauro Ziliani
Hi all
I'm working on and mx51evk babbage board. I have a lvds display connected ti disp1 pads. I need to define DI1_DISP_CLK for pad J18 of the BGA (the chip is 19x19mm) I know the pad definition is made by 5+1 values <mux_reg conf_reg input_reg mux_mode input_val CONFIG> I don't find MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK or similar in imx51-pinfunc.h I find MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK defined with this values. #define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0 But I don't know how to use the 5 values. Where I can find some example o detailed info about? MZ |
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Hi Mauro,
you can refer to our IMX6 definitive GPIO guide related to iMX6 in our wiki |
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Mauro Ziliani
Thank you.
Il 13/03/23 08:54, Marco Cavallini ha
scritto:
Hi Mauro, --
linkedin: https://www.linkedin.com/in/mauroziliani |
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Fabio Estevam
Hi Mauro,
On Sun, Mar 12, 2023 at 3:50 PM Mauro Ziliani <mauro@...> wrote: Why? There is no mux option for the DI1_DISP_CLK pin. |
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Mauro Ziliani
Hi Fabio. In the schematic of the board, the pin J18 is connected to lvds transceiver as DI1_DISP_CLK. I compared the size of the chip and I see there 2 versions: 13x13 mm where J18 is DI1_PIN2, while in the 19x19 J18 is DI1_DISP_CLK.
Il 14/03/23 01:39, Fabio Estevam ha
scritto:
Hi Mauro, On Sun, Mar 12, 2023 at 3:50 PM Mauro Ziliani <mauro@...> wrote:Hi all I'm working on and mx51evk babbage board. I have a lvds display connected ti disp1 pads. I need to define DI1_DISP_CLK for pad J18 of the BGA (the chip is 19x19mm)Why? There is no mux option for the DI1_DISP_CLK pin. --
linkedin: https://www.linkedin.com/in/mauroziliani |
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Fabio Estevam
Hi Mauro,
On Tue, Mar 28, 2023 at 6:51 AM Mauro Ziliani <mauro@...> wrote: DI1_DISP_CLK is also used on the imx51-evk. I don't understand why you want to include DI1_DISP_CLK into imx51-pinfunc.h. The i.MX51 Reference Manual states that the DI1_DISP_CLK has no mux option. It can only work as DI1_DISP_CLK functionality, so you don't need to include it in imx51-pinfunc.h. |
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