<div dir="ltr">Hi Manju,<div><br></div><div>The generated device tree section (that I think is relevant) is here:Â <a href="https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/boards/gfex/prototype3/system-top.dts#L27-L30">https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/boards/gfex/prototype3/system-top.dts#L27-L30</a>Â </div><div><br></div><div><div><font face="monospace"><span style="white-space:pre"> </span>memory {</font></div><div><font face="monospace"><span style="white-space:pre"> </span>device_type = "memory";</font></div><div><font face="monospace"><span style="white-space:pre"> </span>reg = <0x0 0x0 0x0 0x80000000>, <0x00000008 0x00000000 0x0 0x80000000>;</font></div><div><font face="monospace"><span style="white-space:pre"> </span>};</font></div></div><div><font face="monospace"><br></font></div><div>which I think looks correct and specifies from 0x0 -> 0x7FFFFFFF.</div><div><br></div><div>Giordon</div></div><br><div class="gmail_quote"><div dir="ltr">On Wed, Dec 6, 2017 at 2:14 PM Manjukumar Harthikote Matha <<a href="mailto:MANJUKUM@xilinx.com">MANJUKUM@xilinx.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
<br>
> -----Original Message-----<br>
> From: <a href="mailto:meta-xilinx-bounces@yoctoproject.org" target="_blank">meta-xilinx-bounces@yoctoproject.org</a> [mailto:<a href="mailto:meta-xilinx-" target="_blank">meta-xilinx-</a><br>
> <a href="mailto:bounces@yoctoproject.org" target="_blank">bounces@yoctoproject.org</a>] On Behalf Of Giordon Stark<br>
> Sent: Wednesday, December 06, 2017 9:26 AM<br>
> To: <a href="mailto:meta-xilinx@yoctoproject.org" target="_blank">meta-xilinx@yoctoproject.org</a><br>
> Cc: Tang, Shaochun <<a href="mailto:stang@bnl.gov" target="_blank">stang@bnl.gov</a>><br>
> Subject: [meta-xilinx] Wrong DRAM set for custom board using FSBL + u-boot?<br>
><br>
> Hi all,<br>
><br>
> The board I'm using is defined here: <a href="https://github.com/kratsg/meta-" rel="noreferrer" target="_blank">https://github.com/kratsg/meta-</a><br>
> l1calo/blob/master/conf/machine/gfex-prototype3.conf but I'm noticing that the<br>
> DRAM reported by U-Boot is set to 4 GiB. This would be correct for ZCU102, but we<br>
> have 16 GiB DRAM for our custom (v3) board.<br>
><br>
> Where is this setting configured? Is it part of the device tree? If so, why is the device-<br>
> tree-xlnx repository not exporting this correctly?<br>
><br>
<br>
Does the device-tree generated indicate it as 16G? If your HDF has correct settings for 16G, DTG should output correct fragment in the dts/dtsi files. You should compile the u-boot code with this dtb.<br>
<br>
> Thanks!<br>
><br>
> Giordon<br>
</blockquote></div>